/*
 * Copyright (c) 2007-2009, Code Aurora Forum. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef _PROC_COMM_H_
#define _PROC_COMM_H_

#include <common.h>
#define PROC_COMM_BASE SMEM_START

typedef struct {
	uint32_t command;
	uint32_t status;
	uint32_t data1;
	uint32_t data2;
} proc_comm_t;

/* proc_comm commands supported */
enum {
	PROC_COMM_CMD_IDLE = 0x0,
	PROC_COMM_CMD_DONE,
	PROC_COMM_RESET_APPS,
	PROC_COMM_RESET_CHIP,
	PROC_COMM_CONFIG_NAND_MPU,
	PROC_COMM_CONFIG_USB_CLKS,
	PROC_COMM_GET_POWER_ON_STATUS,
	PROC_COMM_GET_WAKE_UP_STATUS,
	PROC_COMM_GET_BATT_LEVEL,
	PROC_COMM_CHG_IS_CHARGING,
	PROC_COMM_POWER_DOWN,
	PROC_COMM_USB_PIN_CONFIG,
	PROC_COMM_USB_PIN_SEL,
	PROC_COMM_SET_RTC_ALARM,
	PROC_COMM_NV_READ,
	PROC_COMM_NV_WRITE,
	PROC_COMM_GET_UUID_HIGH,
	PROC_COMM_GET_UUID_LOW,
	PROC_COMM_GET_HW_ENTROPY,
	PROC_COMM_RPC_GPIO_TLMM_CONFIG_REMOTE,
	PROC_COMM_CLKCTL_RPC_ENABLE,
	PROC_COMM_CLKCTL_RPC_DISABLE,
	PROC_COMM_CLKCTL_RPC_RESET,
	PROC_COMM_CLKCTL_RPC_SET_FLAGS,
	PROC_COMM_CLKCTL_RPC_SET_RATE,
	PROC_COMM_CLKCTL_RPC_MIN_RATE,
	PROC_COMM_CLKCTL_RPC_MAX_RATE,
	PROC_COMM_CLKCTL_RPC_RATE,
	PROC_COMM_CLKCTL_RPC_PLL_REQUEST,
	PROC_COMM_CLKCTL_RPC_ENABLED,
	PROC_COMM_VREG_SWITCH,
	PROC_COMM_VREG_SET_LEVEL,
	PROC_COMM_GPIO_TLMM_CONFIG_GROUP,
	PROC_COMM_GPIO_TLMM_UNCONFIG_GROUP,
	PROC_COMM_NV_WRITE_BYTES_4_7,
	PROC_COMM_CONFIG_DISP,
	PROC_COMM_GET_FTM_BOOT_COUNT,
	PROC_COMM_RPC_GPIO_TLMM_CONFIG_EX,
	PROC_COMM_PM_MPP_CONFIG,
	PROC_COMM_GPIO_IN,
	PROC_COMM_GPIO_OUT,
	PROC_COMM_RESET_MODEM,
	PROC_COMM_RESET_CHIP_IMM,
	PROC_COMM_PM_VID_EN,
	PROC_COMM_VREG_PULLDOWN,
	PROC_COMM_GET_MODEM_VERSION,
	PROC_COMM_CLK_REGIME_SEC_RESET,
	PROC_COMM_CLK_REGIME_SEC_RESET_ASSERT,
	PROC_COMM_CLK_REGIME_SEC_RESET_DEASSERT,
	PROC_COMM_CLK_REGIME_SEC_PLL_REQUEST_WRP,
	PROC_COMM_CLK_REGIME_SEC_ENABLE,
	PROC_COMM_CLK_REGIME_SEC_DISABLE,
	PROC_COMM_CLK_REGIME_SEC_IS_ON,
	PROC_COMM_CLK_REGIME_SEC_SEL_CLK_INV,
	PROC_COMM_CLK_REGIME_SEC_SEL_CLK_SRC,
	PROC_COMM_CLK_REGIME_SEC_SEL_CLK_DIV,
	PROC_COMM_CLK_REGIME_SEC_ICODEC_CLK_ENABLE,
	PROC_COMM_CLK_REGIME_SEC_ICODEC_CLK_DISABLE,
	PROC_COMM_CLK_REGIME_SEC_SEL_SPEED,
	PROC_COMM_CLK_REGIME_SEC_CONFIG_GP_CLK_WRP,
	PROC_COMM_CLK_REGIME_SEC_CONFIG_MDH_CLK_WRP,
	PROC_COMM_CLK_REGIME_SEC_USB_XTAL_ON,
	PROC_COMM_CLK_REGIME_SEC_USB_XTAL_OFF,
	PROC_COMM_CLK_REGIME_SEC_SET_QDSP_DME_MODE,
	PROC_COMM_CLK_REGIME_SEC_SWITCH_ADSP_CLK,
	PROC_COMM_CLK_REGIME_SEC_GET_MAX_ADSP_CLK_KHZ,
	PROC_COMM_CLK_REGIME_SEC_GET_I2C_CLK_KHZ,
	PROC_COMM_CLK_REGIME_SEC_MSM_GET_CLK_FREQ_KHZ,
	PROC_COMM_CLK_REGIME_SEC_SEL_VFE_SRC,
	PROC_COMM_CLK_REGIME_SEC_MSM_SEL_CAMCLK,
	PROC_COMM_CLK_REGIME_SEC_MSM_SEL_LCDCLK,
	PROC_COMM_CLK_REGIME_SEC_VFE_RAIL_OFF,
	PROC_COMM_CLK_REGIME_SEC_VFE_RAIL_ON,
	PROC_COMM_CLK_REGIME_SEC_GRP_RAIL_OFF,
	PROC_COMM_CLK_REGIME_SEC_GRP_RAIL_ON,
	PROC_COMM_CLK_REGIME_SEC_VDC_RAIL_OFF,
	PROC_COMM_CLK_REGIME_SEC_VDC_RAIL_ON,
	PROC_COMM_CLK_REGIME_SEC_LCD_CTRL,
	PROC_COMM_CLK_REGIME_SEC_REGISTER_FOR_CPU_RESOURCE,
	PROC_COMM_CLK_REGIME_SEC_DEREGISTER_FOR_CPU_RESOURCE,
	PROC_COMM_CLK_REGIME_SEC_RESOURCE_REQUEST_WRP,
	PROC_COMM_CLK_REGIME_MSM_SEC_SEL_CLK_OWNER,
	PROC_COMM_CLK_REGIME_SEC_DEVMAN_REQUEST_WRP,
	PROC_COMM_GPIO_CONFIG,
	PROC_COMM_GPIO_CONFIGURE_GROUP,
	PROC_COMM_GPIO_TLMM_SET_PORT,
	PROC_COMM_GPIO_TLMM_CONFIG_EX,
	PROC_COMM_SET_FTM_BOOT_COUNT,
	PROC_COMM_RESERVED0,
	PROC_COMM_RESERVED1,
	PROC_COMM_CUSTOMER_CMD1,
	PROC_COMM_CUSTOMER_CMD2,
	PROC_COMM_CUSTOMER_CMD3,
	PROC_COMM_CLK_REGIME_ENTER_APPSBL_CHG_MODE,
	PROC_COMM_CLK_REGIME_EXIT_APPSBL_CHG_MODE,
	PROC_COMM_CLK_REGIME_SEC_RAIL_DISABLE,
	PROC_COMM_CLK_REGIME_SEC_RAIL_ENABLE,
	PROC_COMM_CLK_REGIME_SEC_RAIL_CONTROL,
	PROC_COMM_SET_SW_WATCHDOG_STATE,
	PROC_COMM_PM_MPP_CONFIG_DIGITAL_INPUT,
	PROC_COMM_PM_MPP_CONFIG_I_SINK,
	PROC_COMM_RESERVED_101,
	PROC_COMM_MSM_HSUSB_PHY_RESET,
	PROC_COMM_GET_BATT_MV_LEVEL,
	PROC_COMM_CHG_USB_IS_PC_CONNECTED,
	PROC_COMM_CHG_USB_IS_CHARGER_CONNECTED,
	PROC_COMM_CHG_USB_IS_DISCONNECTED,
	PROC_COMM_CHG_USB_IS_AVAILABLE,
	PROC_COMM_CLK_REGIME_SEC_MSM_SEL_FREQ,
	PROC_COMM_CLK_REGIME_SEC_SET_PCLK_AXI_POLICY,
	PROC_COMM_NUM_CMDS,
};
/*
 * The following command marks the end of PROC COMM commands for Modem side
 */
#define PROC_COMM_END_CMDS 0xFFFF


/*proc_comm status */
enum {
	PROC_COMM_INVALID_STATUS = 0x0,
	PROC_COMM_READY,
	PROC_COMM_CMD_RUNNING,
	PROC_COMM_CMD_SUCCESS,
	PROC_COMM_CMD_FAIL,
	PROC_COMM_CMD_FAIL_FALSE_RETURNED,
	PROC_COMM_CMD_FAIL_CMD_OUT_OF_BOUNDS_SERVER,
	PROC_COMM_CMD_FAIL_CMD_OUT_OF_BOUNDS_CLIENT,
	PROC_COMM_CMD_FAIL_CMD_UNREGISTERED,
	PROC_COMM_CMD_FAIL_CMD_LOCKED,
	PROC_COMM_CMD_FAIL_SERVER_NOT_YET_READY,
	PROC_COMM_CMD_FAIL_BAD_DESTINATION,
	PROC_COMM_CMD_FAIL_SERVER_RESET,
	PROC_COMM_CMD_FAIL_SMSM_NOT_INIT,
	PROC_COMM_CMD_FAIL_PROC_COMM_BUSY,
	PROC_COMM_CMD_FAIL_PROC_COMM_NOT_INIT,
};

/*---- PROC_COMM_VREG_SWITCH command related ----*/
/* VREG ID for data1 */
/* data2 is either enable or disable */
enum
{
	PM_VREG_MSMA_ID = 0,
	PM_VREG_MSMP_ID = 1,
	PM_VREG_MSME1_ID = 2,   /* Not supported in Panoramix */
	PM_VREG_MSMC1_ID = 3,   /* Not supported in PM6620 */
	PM_VREG_MSMC2_ID = 4,   /* Supported in PM7500 only */
	PM_VREG_GP3_ID = 5,     /* Supported in PM7500 only */
	PM_VREG_MSME2_ID = 6,   /* Supported in PM7500 and Panoramix only */
	PM_VREG_GP4_ID = 7,     /* Supported in PM7500 only */
	PM_VREG_GP1_ID = 8,     /* Supported in PM7500 and Han only */
	PM_VREG_TCXO_ID = 9,
	PM_VREG_PA_ID = 10,
	PM_VREG_RFTX_ID = 11,
	PM_VREG_RFRX1_ID = 12,
	PM_VREG_RFRX2_ID = 13,
	PM_VREG_SYNT_ID = 14,
	PM_VREG_WLAN_ID = 15,
	PM_VREG_USB_ID = 16,
	PM_VREG_BOOST_ID = 17,
	PM_VREG_MMC_ID = 18,
	PM_VREG_RUIM_ID = 19,
	PM_VREG_MSMC0_ID = 20,  /* Supported in PM6610 only */
	PM_VREG_GP2_ID = 21,    /* Supported in PM7500 and Han only */
	PM_VREG_GP5_ID = 22,    /* Supported in PM7500 only */
	PM_VREG_GP6_ID = 23,    /* Supported in PM7500 only */
	PM_VREG_RF_ID = 24,
	PM_VREG_RF_VCO_ID = 25,
	PM_VREG_MPLL_ID = 26,
	PM_VREG_S2_ID = 27,
	PM_VREG_S3_ID = 28,
	PM_VREG_RFUBM_ID = 29,
	PM_VREG_NCP_ID = 30,
	PM_VREG_RF2_ID = 31,
	PM_VREG_RFA_ID = 32,
	PM_VREG_CDC2_ID = 33,
	PM_VREG_RFTX2_ID = 34,
	PM_VREG_USIM_ID = 35,
	PM_VREG_USB2P6_ID = 36,
	PM_VREG_USB3P3_ID = 37,
	PM_VREG_ID_INVALID = 38,

	/* backward compatible enums only */
	PM_VREG_MSME_ID = PM_VREG_MSME1_ID, 		// 2
	PM_VREG_MSME_BUCK_SMPS_ID = PM_VREG_MSME1_ID, 	// 2
	PM_VREG_MSME1_LDO_ID = PM_VREG_MSME1_ID, 	// 2
	PM_VREG_MSMC_ID = PM_VREG_MSMC1_ID, 		// 3
	PM_VREG_MSMC_LDO_ID = PM_VREG_MSMC1_ID, 	// 3
	PM_VREG_MSMC1_BUCK_SMPS_ID = PM_VREG_MSMC1_ID, 	// 3
	PM_VREG_MSME2_LDO_ID = PM_VREG_MSME2_ID, 	// 6
	PM_VREG_CAM_ID = 8, 			/* PM_VREG_GP1_ID = 8 */
	PM_VREG_MDDI_ID = 21, 			/* PM_VREG_GP2_ID = 21 */
	PM_VREG_RUIM2_ID = 5,                   /* PM_VREG_GP3_ID = 5 */
	PM_VREG_AUX_ID = 7,                     /* PM_VREG_GP4_ID = 7 */
	PM_VREG_AUX2_ID = 22,                   /* PM_VREG_GP5_ID = 22 */
	PM_VREG_BT_ID = 23,                     /* PM_VREG_GP6_ID = 23 */
	PM_VREG_RF1_ID = 24,                    /* PM_VREG_RF_ID = 24 */

};

#define PROC_COMM_ENABLE 1
#define PROC_COMM_DISABLE 0

/* ---- PROC_COMM_PM_MPP_CONFIG command related ----*/
/* MPP pins available */
enum
{
	PM_MPP_1,
	PM_MPP_2,
	PM_MPP_3,
	PM_MPP_4,
	PM_MPP_5,
	PM_MPP_6,
	PM_MPP_7,
	PM_MPP_8,
	PM_MPP_9,
	PM_MPP_10,
	PM_MPP_11,
	PM_MPP_12,
	PM_MPP_13,
	PM_MPP_14,
	PM_MPP_15,
	PM_MPP_16,
	PM_MPP_17,
	PM_MPP_18,
	PM_MPP_19,
	PM_MPP_20,
	PM_MPP_21,
	PM_MPP_22,
	PM_MPP_INVALID,
	PM_NUM_MPP_HAN = PM_MPP_4 + 1, 		/* Max num of MPP's for PM7500 */
	PM_NUM_MPP_PM7500 = PM_MPP_22 + 1, 	/* Max num of MPP's for PM6650 */
	PM_NUM_MPP_PM6650 = PM_MPP_12 + 1,	/* Max num of MPP's for PANORAMIX and PM6640 */
	PM_NUM_MPP_PANORAMIX = PM_MPP_2 + 1,
	PM_NUM_MPP_PM6640 = PM_NUM_MPP_PANORAMIX,
	PM_NUM_MPP_PM6620 = PM_NUM_MPP_PANORAMIX
};

/* MPP Logic Level */
enum
{
	PM_MPP__DLOGIC__LVL_MSME,
	PM_MPP__DLOGIC__LVL_MSMP,
	PM_MPP__DLOGIC__LVL_RUIM,
	PM_MPP__DLOGIC__LVL_MMC,
	PM_MPP__DLOGIC__LVL_VDD,
	PM_MPP__DLOGIC__LVL_INVALID
};

/* MPP Output control */
enum
{

	PM_MPP__DLOGIC_OUT__CTRL_LOW, 	/* MPP OUTPUT= LOGIC LOW */
	PM_MPP__DLOGIC_OUT__CTRL_HIGH, 	/* MPP OUTPUT= LOGIC HIGH */
	PM_MPP__DLOGIC_OUT__CTRL_MPP, 	/* MPP OUTPUT= CORRESPONDING MPP INPUT */
	PM_MPP__DLOGIC_OUT__CTRL_NOT_MPP, /* MPP OUTPUT= CORRESPONDING INVERTED MPP INPUT*/
	PM_MPP__DLOGIC_OUT__CTRL_INVALID,
};

/*---- PROC_COMM_RPC_GPIO_TLMM_CONFIG_EX related ----*/
/* GPIO TLMM: Function -- GPIO specific */

/* GPIO TLMM: Direction */
enum {
	GPIO_INPUT,
	GPIO_OUTPUT,
};

/* GPIO TLMM: Pullup/Pulldown */
enum {
	GPIO_NO_PULL,
	GPIO_PULL_DOWN,
	GPIO_KEEPER,
	GPIO_PULL_UP,
};

/* GPIO TLMM: Drive Strength */
enum {
	GPIO_2MA,
	GPIO_4MA,
	GPIO_6MA,
	GPIO_8MA,
	GPIO_10MA,
	GPIO_12MA,
	GPIO_14MA,
	GPIO_16MA,
};

enum {
	GPIO_ENABLE,
	GPIO_DISABLE,
};

#define GPIO_CFG(gpio, func, dir, pull, drvstr) \
	((((gpio) & 0x3FF) << 4)        |	  \
	 ((func) & 0xf)                  |	  \
	 (((dir) & 0x1) << 14)           |	  \
	 (((pull) & 0x3) << 15)          |	  \
	 (((drvstr) & 0xF) << 17))

/*---- Clk control related ----*/
enum
{
	PROC_COMM_ACPU_CLK,	  /* Applications processor clock */
	PROC_COMM_ADM_CLK,	  /* Applications data mover clock */
	PROC_COMM_ADSP_CLK,	  /* ADSP clock */
	PROC_COMM_EBI1_CLK,	  /* External bus interface 1 clock */
	PROC_COMM_EBI2_CLK,	  /* External bus interface 2 clock */
	PROC_COMM_ECODEC_CLK,	  /* External CODEC clock */
	PROC_COMM_EMDH_CLK,	  /* External MDDI host clock */
	PROC_COMM_GP_CLK,	  /* General purpose clock */
	PROC_COMM_GRP_CLK,	  /* Graphics clock */
	PROC_COMM_I2C_CLK,	  /* I2C clock */
	PROC_COMM_ICODEC_RX_CLK,  /* Internal CODEX RX clock */
	PROC_COMM_ICODEC_TX_CLK,  /* Internal CODEX TX clock */
	PROC_COMM_IMEM_CLK,	  /* Internal graphics memory clock */
	PROC_COMM_MDC_CLK,	  /* MDDI client clock */
	PROC_COMM_MDP_CLK,	  /* Mobile display processor clock */
	PROC_COMM_PBUS_CLK,	  /* Peripheral bus clock */
	PROC_COMM_PCM_CLK,	  /* PCM clock */
	PROC_COMM_PMDH_CLK,	  /* Primary MDDI host clock */
	PROC_COMM_SDAC_CLK,	  /* Stereo DAC clock */
	PROC_COMM_SDC1_CLK,	  /* Secure Digital Card clocks */
	PROC_COMM_SDC1_PCLK,
	PROC_COMM_SDC2_CLK,
	PROC_COMM_SDC2_PCLK,
	PROC_COMM_SDC3_CLK,
	PROC_COMM_SDC3_PCLK,
	PROC_COMM_SDC4_CLK,
	PROC_COMM_SDC4_PCLK,
	PROC_COMM_TSIF_CLK,	  /* Transport Stream Interface clocks */
	PROC_COMM_TSIF_REF_CLK,
	PROC_COMM_TV_DAC_CLK,	  /* TV clocks */
	PROC_COMM_TV_ENC_CLK,
	PROC_COMM_UART1_CLK,	  /* UART clocks */
	PROC_COMM_UART2_CLK,
	PROC_COMM_UART3_CLK,
	PROC_COMM_UART1DM_CLK,
	PROC_COMM_UART2DM_CLK,
	PROC_COMM_USB_HS_CLK,	  /* High speed USB core clock */
	PROC_COMM_USB_HS_PCLK,	  /* High speed USB pbus clock */
	PROC_COMM_USB_OTG_CLK,	  /* Full speed USB clock */
	PROC_COMM_VDC_CLK,	  /* Video controller clock */
	PROC_COMM_VFE_MDC_CLK,	  /* Camera / Video Front End clock */
	PROC_COMM_VFE_CLK,	  /* VFE MDDI client clock */
	PROC_COMM_MDP_LCDC_PCLK_CLK,
	PROC_COMM_MDP_LCDC_PAD_PCLK_CLK,
	PROC_COMM_MDP_VSYNC_CLK,
	PROC_COMM_SPI_CLK,
	PROC_COMM_VFE_AXI_CLK,
	PROC_COMM_USB_HS2_CLK,	  /* High speed USB 2 core clock */
	PROC_COMM_USB_HS2_PCLK,	  /* High speed USB 2 pbus clock */
	PROC_COMM_USB_HS3_CLK,	  /* High speed USB 3 core clock */
	PROC_COMM_USB_HS3_PCLK,	  /* High speed USB 3 pbus clock */
	PROC_COMM_GRP_PCLK,	  /* Graphics pbus clock */
	PROC_COMM_NR_CLKS,
};

int proc_comm_wait_for_modem_ready(void);
void proc_comm_init(void);

#endif /*_PROC_COMM_H*/
